1. Technical Field
The present invention relates generally to data processing systems, and more particularly, to data processing systems having a capability to record information regarding executional delays, such as stall conditions.
2. Description of the Related Art
Data processing systems, and in particular superscalar and pipelined processors, frequently experience “stall conditions” or “stalls,” which are events that delay the completion of one or more instructions by a clock cycle or more. Stalls may occur for various reasons, such as branch mispredictions (which typically require a lengthy “pipeline flush” to resolve), delay in accessing data (e.g., due to cache misses), and high latency instructions (such as many floating point operations).
While some stalls are unavoidable, it is generally desirable to minimize the number of stall conditions a processor incurs whenever possible, as a significant number of stalls can seriously degrade processor performance. As with many aspects of the computer architecture field, the number of stalls incurred by a processor is a function of both the processor's design and the design of the software being executed on the processor (which is often, in turn, largely dictated by the design of the compiler used to produce the software). The design of either hardware or software for a given platform so as to minimize stalls, not surprisingly, requires the hardware or software engineer to obtain a fair level of insight into the causes behind stalls and the extent to which particular instructions lead to performance degrading stall conditions.
Previous work in this area, such as the herein-incorporated U.S. Pat. No. 7,047,398 and U.S. patent application Ser. No. 11/753,005 has focused on determining a basic cause of a stall emanating from a group of instructions in a superscalar processor. However, the current state of the art does not provide a way to monitor the stall-related characteristics of individual instructions.
What is needed, therefore, is a method and apparatus for monitoring a particular instruction (or class of instruction's) propensity to cause stalls. The present invention provides a solution to this and other problems, and offers other advantages over previous solutions.